Lattice Semiconductor ISPLSI1016-90LJ: An In-Depth Technical Overview of the High-Density Programmable Logic Device
The Lattice Semiconductor ISPLSI1016-90LJ represents a pivotal component in the lineage of High-Density Programmable Logic Devices (HDPLDs). As a member of the pioneering ispLSI 1000E family, this device combines in-system programmability (ISP) with a robust architecture, making it a versatile solution for a wide array of digital logic applications. This article provides a detailed technical examination of its architecture, key features, and target use cases.
Architectural Core: The Generic Logic Block (GLB)
At the heart of the ISPLSI1016-90LJ lies a highly structured architecture built around Generic Logic Blocks (GLBs). The device contains 16 GLBs, each capable of implementing complex combinatorial and sequential logic functions. Each GLB is comprised of 18 macrocells, featuring programmable AND/OR arrays and configurable registers that can be set to operate as D, T, JK, or SR flip-flops. This flexibility allows designers to efficiently implement state machines, counters, and data processing units within a single, unified fabric.
Global Routing Pool (GRP) and I/O Flexibility
A key to the device's performance is its Global Routing Pool (GRP), a centralized interconnect resource that provides a deterministic and predictable signal path between all GLBs and Input/Output pins. This structure minimizes timing delays and simplifies the design process. The ISPLSI1016-90LJ features 36 I/O pins, each connected to an I/O cell that is linked to the GRP. These I/O cells offer programmable control over slew rate and pull-up resistors, allowing for optimized signal integrity and direct interfacing with various logic families (e.g., TTL, CMOS).
In-System Programmability (ISP) and Speed
A defining characteristic of this device is its 5V in-system programmability (ISP). Utilizing a simple 5-wire interface, the device can be reprogrammed directly on the printed circuit board (PCB), drastically reducing development cycles, facilitating rapid prototyping, and enabling field upgrades without physical hardware changes. The "-90LJ" suffix denotes a 90 MHz maximum operating frequency, indicating its capability to handle high-speed logic operations, which was a significant performance metric for its time.
Target Applications and Design Role
The ISPLSI1016-90LJ, with its equivalent density of approximately 2,000 PLD gates, was designed to serve as a "glue logic" consolidator. Its primary role was to integrate multiple discrete standard logic ICs (such as 74-series chips) into a single, programmable device. This consolidation resulted in reduced board space, lower overall system cost, improved reliability, and enhanced design security. Typical applications included:
System level integration and address decoding in microprocessors.
High-speed state machine and controller design.
Data routing and bus interfacing in communication systems.
Industrial control and automotive electronics.
The Lattice ispLSI1016-90LJ stands as a testament to the evolution of programmable logic. It successfully merged high-density architecture with the revolutionary convenience of in-system programmability, offering designers a powerful tool for system integration. While newer families have surpassed it in density and power efficiency, its architectural principles of a GRP and flexible GLBs remain foundational. For legacy system maintenance or educational purposes, understanding this device provides critical insight into the history and practical application of CPLD technology.
Keywords:
In-System Programmability (ISP)
High-Density Programmable Logic Device (HDPLD)
Generic Logic Block (GLB)
Global Routing Pool (GRP)
Glue Logic
